Even Numbers Filter - Verilog Typing CST Test

Mode:

Duration:

module EvenNumbers(
	output reg [31:0] evens [0:4]
);

	reg [31:0] nums [0:9];
	integer i, idx;

	initial begin
		nums = '{1,2,3,4,5,6,7,8,9,10};
	end

	always @(*) begin
		idx = 0;
		for(i=0;i<10;i=i+1) begin
		if(nums[i] % 2 == 0) begin
		evens[idx] = nums[i];
		idx = idx + 1;
		end
		end
	end

endmoduleCoding works best on desktop or with an external keyboard.

Even Numbers Filter — Verilog Code

Outputs even numbers from a fixed array.

module EvenNumbers(
	output reg [31:0] evens [0:4]
);

	reg [31:0] nums [0:9];
	integer i, idx;

	initial begin
		nums = '{1,2,3,4,5,6,7,8,9,10};
	end

	always @(*) begin
		idx = 0;
		for(i=0;i<10;i=i+1) begin
		if(nums[i] % 2 == 0) begin
		evens[idx] = nums[i];
		idx = idx + 1;
		end
		end
	end

endmodule

Verilog Language Guide

Verilog is a hardware description language (HDL) used to model, simulate, and design digital circuits such as CPUs, FPGAs, ASICs, and SoCs. Known for its C-like syntax, simplicity, and dominance in commercial chip design.

Primary Use Cases

▸ASIC and SoC design
▸FPGA development
▸Digital logic design (ALUs, FSMs, DSP blocks)
▸Processor architecture modeling
▸Hardware simulation & verification

Notable Features

▸C-like syntax (begin/end, if, case)
▸Concurrent and procedural blocks
▸Gate-level, RTL, and behavioral modeling
▸Synthesizable hardware constructs
▸Rich simulation capabilities

Origin & Creator

Developed in 1984 by Phil Moorby at Gateway Design Automation; standardized as IEEE 1364.

Industrial Note

Verilog powers most commercial semiconductor chips - including CPUs, GPUs, networking ASICs, and FPGA IP cores.

Quick Explain

▸Verilog describes actual digital hardware through concurrent logic.
▸Its syntax is compact and similar to C, making it easier for beginners.
▸Widely used in semiconductor, embedded systems, and FPGA industries.

Core Features

▸Modules (hardware building blocks)
▸Always blocks for sequential/combinational logic
▸Blocking vs non-blocking assignments
▸Parameters for configurable hardware
▸Testbenches with $display, $monitor, $dumpvars

Learning Path

▸Start with basic modules and signals
▸Learn reg vs wire behavior
▸Practice always blocks and testbenches
▸Build FSMs, ALUs, UARTs
▸Move into CPU design or FPGA synthesis

Practical Examples

▸LED blink module
▸4-bit ripple-carry adder
▸Finite State Machine
▸UART communication module
▸Pipelined ALU

Comparisons

▸More compact than VHDL
▸Less strict typing than VHDL
▸Easier for beginners than VHDL
▸Inferior verification features vs SystemVerilog
▸More widely used in ASIC industry than VHDL

Strengths

▸Easy to learn due to C-like syntax
▸Fast development and prototyping
▸Ideal for RTL design
▸Excellent industry tool support
▸Core language behind many silicon chips

Limitations

▸Weaker type system than VHDL
▸Allows sloppy coding if not careful
▸Race conditions possible with poor coding
▸Limited structured abstraction vs SystemVerilog
▸Less strict, easier to write buggy designs

When NOT to Use

▸Very large safety-critical systems (VHDL preferred)
▸Complex verification (SystemVerilog UVM preferred)
▸Analog/mixed-signal (use Verilog-AMS)
▸Ultra-high-level hardware modeling
▸Designs requiring strict type safety

Cheat Sheet

▸module NAME (input, output);
▸assign y = a & b;
▸always @(*) begin ... end
▸always @(posedge clk) begin ... end
▸<= non-blocking for sequential, = blocking for combinational

FAQ

▸Is Verilog still used?
▸Yes - it dominates ASIC and commercial chip design.
▸Is Verilog easier than VHDL?
▸Yes - simpler syntax and fewer rules.
▸Can Verilog design processors?
▸Absolutely - many open-source CPUs use Verilog.
▸Should I learn Verilog or SystemVerilog?
▸Verilog for basics, SystemVerilog for professional verification.

30-Day Skill Plan

▸Week 1: Syntax + combinational logic
▸Week 2: Sequential logic + FSMs
▸Week 3: Testbenches + waveforms
▸Week 4: Pipelining + FPGA synthesis

Final Summary

▸Verilog is foundational for digital hardware design.
▸Fast, simple, and widely used for ASIC/FPGA development.
▸Ideal for RTL design and simulation.
▸A top skill for semiconductor, embedded, and FPGA careers.

Project Structure

▸src/ - Verilog source files
▸tb/ - testbenches
▸constraints/ - pin mapping
▸simulation/ - waveform dump files
▸ip/ - reusable IP blocks

Monetization

▸FPGA design consulting
▸ASIC/SoC development roles
▸Creating IP cores for sale
▸Embedded hardware engineering
▸Semiconductor verification services

Productivity Tips

▸Use templates for modules/testbenches
▸Automate simulation scripts
▸Use non-blocking for sequential logic
▸Always review waveforms
▸Leverage parameters for generic design

Basic Concepts

▸Modules and ports
▸Reg vs wire
▸Always blocks
▸Blocking (=) vs non-blocking (<=)
▸Continuous assignments

Official Docs

▸IEEE 1364 Verilog Standard
▸IEEE Synthesis Subset Guidelines
▸Vendor tool documentation

More Verilog Typing Exercises

Verilog Counter and Theme Toggle Verilog Simple Addition Verilog Factorial Verilog Fibonacci Sequence Verilog Max of Two Numbers Verilog Array Sum Verilog String Concatenation Verilog Conditional Counter Increment Verilog Counter With Reset and Enable

Practice Other Languages

C React Python C++Rust TypeScript Kotlin PHP Java C#Ruby Mql Cql N1ql Cypher

module EvenNumbers(
output reg [31:0] evens [0:4]
);

reg [31:0] nums [0:9];
integer i, idx;

initial begin
nums = '{1,2,3,4,5,6,7,8,9,10};
end

always @(*) begin
idx = 0;
for(i=0;i<10;i=i+1) begin
if(nums[i] % 2 == 0) begin
evens[idx] = nums[i];
idx = idx + 1;
end
end
end

endmodule

Coding works best on desktop or with an external keyboard.

Even Numbers Filter — Verilog Code

Outputs even numbers from a fixed array.

module EvenNumbers( output reg [31:0] evens [0:4] ); reg [31:0] nums [0:9]; integer i, idx; initial begin nums = '{1,2,3,4,5,6,7,8,9,10}; end always @(*) begin idx = 0; for(i=0;i<10;i=i+1) begin if(nums[i] % 2 == 0) begin evens[idx] = nums[i]; idx = idx + 1; end end end endmodule

Verilog Language Guide

Primary Use Cases

▸ASIC and SoC design
▸FPGA development
▸Digital logic design (ALUs, FSMs, DSP blocks)
▸Processor architecture modeling
▸Hardware simulation & verification

Notable Features

▸C-like syntax (begin/end, if, case)
▸Concurrent and procedural blocks
▸Gate-level, RTL, and behavioral modeling
▸Synthesizable hardware constructs
▸Rich simulation capabilities

Origin & Creator

Developed in 1984 by Phil Moorby at Gateway Design Automation; standardized as IEEE 1364.

Industrial Note

Verilog powers most commercial semiconductor chips - including CPUs, GPUs, networking ASICs, and FPGA IP cores.