Learn VERILOG with Real Code Examples

Verilog describes actual digital hardware through concurrent logic.

Its syntax is compact and similar to C, making it easier for beginners.

Widely used in semiconductor, embedded systems, and FPGA industries.

Modules (hardware building blocks)

Always blocks for sequential/combinational logic

Blocking vs non-blocking assignments

Parameters for configurable hardware

Testbenches with $display, $monitor, $dumpvars

Modules and ports

Reg vs wire

Always blocks

Blocking (=) vs non-blocking (<=)

Continuous assignments

src/ - Verilog source files

tb/ - testbenches

constraints/ - pin mapping

simulation/ - waveform dump files

ip/ - reusable IP blocks

Write module (.v file)

Write testbench (.v)

Compile with simulation tool

Run simulation to verify behavior

Synthesize with FPGA/ASIC tools

Beginner: gates, multiplexers, counters

Intermediate: FSMs, UARTs, simple CPUs

Advanced: pipelined processors, DSP cores

Expert: SoCs, RISC-V implementations, ASIC tape-out designs

More compact than VHDL

Less strict typing than VHDL

Easier for beginners than VHDL

Inferior verification features vs SystemVerilog

More widely used in ASIC industry than VHDL

1984 – Verilog created

1989 – Gateway acquired by Cadence

1995 – IEEE 1364 standardization

2001 – Enhancements in Verilog-2001

2005+ – SystemVerilog becomes successor

Module: Hardware block

Reg: Procedural storage

Wire: Physical connection

Always block: Hardware behavior

Sensitivity list: Trigger conditions