Array Sum - Verilog Typing CST Test
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Array Sum — Verilog Code
Sums elements of a fixed array.
module ArraySum(
output reg [31:0] sum
);
reg [31:0] nums [0:4];
integer i;
initial begin
nums[0] = 1; nums[1] = 2; nums[2] = 3; nums[3] = 4; nums[4] = 5;
end
always @(*) begin
sum = 0;
for(i=0;i<5;i=i+1) begin
sum = sum + nums[i];
end
end
endmoduleVerilog Language Guide
Verilog is a hardware description language (HDL) used to model, simulate, and design digital circuits such as CPUs, FPGAs, ASICs, and SoCs. Known for its C-like syntax, simplicity, and dominance in commercial chip design.
Primary Use Cases
- ▸ASIC and SoC design
- ▸FPGA development
- ▸Digital logic design (ALUs, FSMs, DSP blocks)
- ▸Processor architecture modeling
- ▸Hardware simulation & verification
Notable Features
- ▸C-like syntax (begin/end, if, case)
- ▸Concurrent and procedural blocks
- ▸Gate-level, RTL, and behavioral modeling
- ▸Synthesizable hardware constructs
- ▸Rich simulation capabilities
Origin & Creator
Developed in 1984 by Phil Moorby at Gateway Design Automation; standardized as IEEE 1364.
Industrial Note
Verilog powers most commercial semiconductor chips - including CPUs, GPUs, networking ASICs, and FPGA IP cores.