Factorial - Verilog Typing CST Test

Loading…

Factorial — Verilog Code

Calculates factorial of 5 using a sequential always block.

module Factorial(
	input clk,
	input reset,
	output reg [31:0] fact
);

	reg [31:0] counter;

	always @(posedge clk or posedge reset) begin
		if(reset) begin
		fact <= 1;
		counter <= 1;
		end else begin
		if(counter <= 5) begin
		fact <= fact * counter;
		counter <= counter + 1;
		end
		end
	end

endmodule

Verilog Language Guide

Verilog is a hardware description language (HDL) used to model, simulate, and design digital circuits such as CPUs, FPGAs, ASICs, and SoCs. Known for its C-like syntax, simplicity, and dominance in commercial chip design.

Primary Use Cases

▸ASIC and SoC design
▸FPGA development
▸Digital logic design (ALUs, FSMs, DSP blocks)
▸Processor architecture modeling
▸Hardware simulation & verification

Notable Features

▸C-like syntax (begin/end, if, case)
▸Concurrent and procedural blocks
▸Gate-level, RTL, and behavioral modeling
▸Synthesizable hardware constructs
▸Rich simulation capabilities

Origin & Creator

Developed in 1984 by Phil Moorby at Gateway Design Automation; standardized as IEEE 1364.

Industrial Note

Verilog powers most commercial semiconductor chips - including CPUs, GPUs, networking ASICs, and FPGA IP cores.

More Verilog Typing Exercises

Verilog Counter and Theme Toggle Verilog Simple Addition Verilog Fibonacci Sequence Verilog Max of Two Numbers Verilog Array Sum Verilog Even Numbers Filter Verilog String Concatenation Verilog Conditional Counter Increment Verilog Counter With Reset and Enable

Practice Other Languages

C React Python C++Rust TypeScript Kotlin PHP Java C#Ruby Mql Cql N1ql Cypher