Fibonacci Sequence - Vhdl Typing CST Test
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Fibonacci Sequence — Vhdl Code
Generates first 10 Fibonacci numbers using signals and an array.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Fibonacci is
Port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
fib_out : out INTEGER_VECTOR(0 to 9)
);
end Fibonacci;
architecture Behavioral of Fibonacci is
signal fib : INTEGER_VECTOR(0 to 9);
begin
process(clk, reset)
begin
if reset = '1' then
fib(0) <= 0;
fib(1) <= 1;
elsif rising_edge(clk) then
for i in 2 to 9 loop
fib(i) <= fib(i-1) + fib(i-2);
end loop;
end if;
end process;
fib_out <= fib;
end Behavioral;Vhdl Language Guide
VHDL (VHSIC Hardware Description Language) is a strongly typed, concurrent hardware description language used to model, simulate, and synthesize digital systems such as FPGAs, ASICs, and SoCs. Designed for reliability, formal precision, and hardware-level abstraction.
Primary Use Cases
- ▸FPGA design and development
- ▸ASIC/SoC prototyping
- ▸Digital logic design (counters, FSMs, datapaths)
- ▸High-reliability hardware (military/aerospace)
- ▸Hardware verification and simulation
Notable Features
- ▸Strong static typing
- ▸Concurrency built into the language
- ▸Timing-accurate simulation
- ▸Synthesizable constructs for hardware generation
- ▸Package- and library-based modularity
Origin & Creator
Developed in the early 1980s by the U.S. Department of Defense (DoD) under the VHSIC program; standardized as IEEE 1076.
Industrial Note
You’ll find VHDL embedded in aerospace avionics, defense-grade chips, satellite systems, telecom switching, and radiation-hardened FPGA applications.