Even Numbers Filter - Vhdl Typing CST Test

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Even Numbers Filter — Vhdl Code

Outputs even numbers from a fixed array.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity EvenNumbers is
	Port (
		evens_out : out INTEGER_VECTOR(0 to 4)
	);
end EvenNumbers;

architecture Behavioral of EvenNumbers is
	signal nums : INTEGER_VECTOR(0 to 9) := (1,2,3,4,5,6,7,8,9,10);
	signal evens : INTEGER_VECTOR(0 to 4);
begin
	process(nums)
		variable idx : INTEGER := 0;
	begin
		idx := 0;
		for i in 0 to 9 loop
		if nums(i) mod 2 = 0 then
		evens(idx) <= nums(i);
		idx := idx + 1;
		end if;
		end loop;
	end process;

	evens_out <= evens;
end Behavioral;

Vhdl Language Guide

VHDL (VHSIC Hardware Description Language) is a strongly typed, concurrent hardware description language used to model, simulate, and synthesize digital systems such as FPGAs, ASICs, and SoCs. Designed for reliability, formal precision, and hardware-level abstraction.

Primary Use Cases

▸FPGA design and development
▸ASIC/SoC prototyping
▸Digital logic design (counters, FSMs, datapaths)
▸High-reliability hardware (military/aerospace)
▸Hardware verification and simulation

Notable Features

▸Strong static typing
▸Concurrency built into the language
▸Timing-accurate simulation
▸Synthesizable constructs for hardware generation
▸Package- and library-based modularity

Origin & Creator

Developed in the early 1980s by the U.S. Department of Defense (DoD) under the VHSIC program; standardized as IEEE 1076.

Industrial Note

You’ll find VHDL embedded in aerospace avionics, defense-grade chips, satellite systems, telecom switching, and radiation-hardened FPGA applications.

More Vhdl Typing Exercises

VHDL Counter and Theme Toggle VHDL Simple Addition VHDL Factorial VHDL Fibonacci Sequence VHDL Max of Two Numbers VHDL Array Sum VHDL String Concatenation VHDL Conditional Counter Increment VHDL Conditional Counter Increment

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Even Numbers Filter — Vhdl Code

Outputs even numbers from a fixed array.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity EvenNumbers is Port ( evens_out : out INTEGER_VECTOR(0 to 4) ); end EvenNumbers; architecture Behavioral of EvenNumbers is signal nums : INTEGER_VECTOR(0 to 9) := (1,2,3,4,5,6,7,8,9,10); signal evens : INTEGER_VECTOR(0 to 4); begin process(nums) variable idx : INTEGER := 0; begin idx := 0; for i in 0 to 9 loop if nums(i) mod 2 = 0 then evens(idx) <= nums(i); idx := idx + 1; end if; end loop; end process; evens_out <= evens; end Behavioral;

Vhdl Language Guide

Primary Use Cases

▸FPGA design and development
▸ASIC/SoC prototyping
▸Digital logic design (counters, FSMs, datapaths)
▸High-reliability hardware (military/aerospace)
▸Hardware verification and simulation

Notable Features

▸Strong static typing
▸Concurrency built into the language
▸Timing-accurate simulation
▸Synthesizable constructs for hardware generation
▸Package- and library-based modularity

Origin & Creator

Developed in the early 1980s by the U.S. Department of Defense (DoD) under the VHSIC program; standardized as IEEE 1076.

Industrial Note

You’ll find VHDL embedded in aerospace avionics, defense-grade chips, satellite systems, telecom switching, and radiation-hardened FPGA applications.