Factorial - Vhdl Typing CST Test

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Factorial — Vhdl Code

Calculates factorial of 5 using a clocked process.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Factorial is
	Port (
		clk : in STD_LOGIC;
		reset : in STD_LOGIC;
		fact_out : out INTEGER
	);
end Factorial;

architecture Behavioral of Factorial is
	signal fact : INTEGER := 1;
	signal counter : INTEGER := 1;
	constant N : INTEGER := 5;
begin

	process(clk, reset)
	begin
		if reset = '1' then
		fact <= 1;
		counter <= 1;
		elsif rising_edge(clk) then
		if counter <= N then
		fact <= fact * counter;
		counter <= counter + 1;
		end if;
		end if;
	end process;

	fact_out <= fact;
end Behavioral;

Vhdl Language Guide

VHDL (VHSIC Hardware Description Language) is a strongly typed, concurrent hardware description language used to model, simulate, and synthesize digital systems such as FPGAs, ASICs, and SoCs. Designed for reliability, formal precision, and hardware-level abstraction.

Primary Use Cases

▸FPGA design and development
▸ASIC/SoC prototyping
▸Digital logic design (counters, FSMs, datapaths)
▸High-reliability hardware (military/aerospace)
▸Hardware verification and simulation

Notable Features

▸Strong static typing
▸Concurrency built into the language
▸Timing-accurate simulation
▸Synthesizable constructs for hardware generation
▸Package- and library-based modularity

Origin & Creator

Developed in the early 1980s by the U.S. Department of Defense (DoD) under the VHSIC program; standardized as IEEE 1076.

Industrial Note

You’ll find VHDL embedded in aerospace avionics, defense-grade chips, satellite systems, telecom switching, and radiation-hardened FPGA applications.

More Vhdl Typing Exercises

VHDL Counter and Theme Toggle VHDL Simple Addition VHDL Fibonacci Sequence VHDL Max of Two Numbers VHDL Array Sum VHDL Even Numbers Filter VHDL String Concatenation VHDL Conditional Counter Increment VHDL Conditional Counter Increment

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Factorial — Vhdl Code

Calculates factorial of 5 using a clocked process.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Factorial is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; fact_out : out INTEGER ); end Factorial; architecture Behavioral of Factorial is signal fact : INTEGER := 1; signal counter : INTEGER := 1; constant N : INTEGER := 5; begin process(clk, reset) begin if reset = '1' then fact <= 1; counter <= 1; elsif rising_edge(clk) then if counter <= N then fact <= fact * counter; counter <= counter + 1; end if; end if; end process; fact_out <= fact; end Behavioral;

Vhdl Language Guide

Primary Use Cases

▸FPGA design and development
▸ASIC/SoC prototyping
▸Digital logic design (counters, FSMs, datapaths)
▸High-reliability hardware (military/aerospace)
▸Hardware verification and simulation

Notable Features

▸Strong static typing
▸Concurrency built into the language
▸Timing-accurate simulation
▸Synthesizable constructs for hardware generation
▸Package- and library-based modularity

Origin & Creator

Developed in the early 1980s by the U.S. Department of Defense (DoD) under the VHSIC program; standardized as IEEE 1076.

Industrial Note

You’ll find VHDL embedded in aerospace avionics, defense-grade chips, satellite systems, telecom switching, and radiation-hardened FPGA applications.