Learn VERILOG with Real Code Examples

module Counter(
    input clk,
    input reset,
    output reg [31:0] count,
    output reg isDark
);

    always @(posedge clk or posedge reset) begin
        if (reset) begin
        count <= 0;
        isDark <= 0;
        end else begin
        count <= count + 1;
        isDark <= ~isDark;
        end
    end

endmodule

Demonstrates a simple counter with theme toggle using Verilog registers and always blocks.

module AddProgram(
    input [31:0] a,
    input [31:0] b,
    output reg [31:0] sum
);

    always @(*) begin
        sum = a + b;
    end

endmodule

Adds two numbers using registers and outputs the result.

module Factorial(
    input clk,
    input reset,
    output reg [31:0] fact
);

    reg [31:0] counter;

    always @(posedge clk or posedge reset) begin
        if(reset) begin
        fact <= 1;
        counter <= 1;
        end else begin
        if(counter <= 5) begin
        fact <= fact * counter;
        counter <= counter + 1;
        end
        end
    end

endmodule

Calculates factorial of 5 using a sequential always block.

module Fibonacci(
    input clk,
    input reset,
    output reg [31:0] fib [0:9]
);

    integer i;

    always @(posedge clk or posedge reset) begin
        if(reset) begin
        fib[0] <= 0;
        fib[1] <= 1;
        end else begin
        for(i=2; i<10; i=i+1) begin
        fib[i] <= fib[i-1] + fib[i-2];
        end
        end
    end

endmodule

Generates first 10 Fibonacci numbers using registers and an array.

module MaxProgram(
    input [31:0] a,
    input [31:0] b,
    output reg [31:0] max
);

    always @(*) begin
        if(a > b) max = a;
        else max = b;
    end

endmodule

Finds the maximum of two numbers.

module ArraySum(
    output reg [31:0] sum
);

    reg [31:0] nums [0:4];
    integer i;

    initial begin
        nums[0] = 1; nums[1] = 2; nums[2] = 3; nums[3] = 4; nums[4] = 5;
    end

    always @(*) begin
        sum = 0;
        for(i=0;i<5;i=i+1) begin
        sum = sum + nums[i];
        end
    end

endmodule

Sums elements of a fixed array.

module EvenNumbers(
    output reg [31:0] evens [0:4]
);

    reg [31:0] nums [0:9];
    integer i, idx;

    initial begin
        nums = '{1,2,3,4,5,6,7,8,9,10};
    end

    always @(*) begin
        idx = 0;
        for(i=0;i<10;i=i+1) begin
        if(nums[i] % 2 == 0) begin
        evens[idx] = nums[i];
        idx = idx + 1;
        end
        end
    end

endmodule

Outputs even numbers from a fixed array.

module ConcatStrings(
    output reg [39:0] result
);

    reg [19:0] str1 = "HELLO";
    reg [19:0] str2 = "WORLD";

    always @(*) begin
        result = {str1, str2};
    end

endmodule

Concatenates two strings using Verilog.

module ConditionalIncrement(
    input clk,
    input reset,
    output reg [31:0] count
);

    always @(posedge clk or posedge reset) begin
        if(reset) count <= 3;
        else if(count < 5) count <= count + 1;
    end

endmodule

Increment counter only if below 5.

module CounterEnable(
    input clk,
    input reset,
    input enable,
    output reg [31:0] count
);

    always @(posedge clk) begin
        if(reset) count <= 0;
        else if(enable) count <= count + 1;
    end

endmodule

Counts with enable signal and synchronous reset.