Learn VHDL with Real Code Examples

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Counter is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        count_out : out INTEGER;
        isDark_out : out STD_LOGIC
    );
end Counter;

architecture Behavioral of Counter is
    signal count : INTEGER := 0;
    signal isDark : STD_LOGIC := '0';
begin

    process(clk, reset)
    begin
        if reset = '1' then
        count <= 0;
        isDark <= '0';
        elsif rising_edge(clk) then
        count <= count + 1;
        isDark <= not isDark;
        end if;
    end process;

    count_out <= count;
    isDark_out <= isDark;

end Behavioral;

Demonstrates a simple counter with theme toggle using VHDL signals and processes.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AddProgram is
    Port (
        a : in INTEGER;
        b : in INTEGER;
        sum_out : out INTEGER
    );
end AddProgram;

architecture Behavioral of AddProgram is
    signal sum : INTEGER := 0;
begin
    sum_out <= a + b;
end Behavioral;

Adds two numbers using signals and outputs the result.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Factorial is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        fact_out : out INTEGER
    );
end Factorial;

architecture Behavioral of Factorial is
    signal fact : INTEGER := 1;
    signal counter : INTEGER := 1;
    constant N : INTEGER := 5;
begin

    process(clk, reset)
    begin
        if reset = '1' then
        fact <= 1;
        counter <= 1;
        elsif rising_edge(clk) then
        if counter <= N then
        fact <= fact * counter;
        counter <= counter + 1;
        end if;
        end if;
    end process;

    fact_out <= fact;
end Behavioral;

Calculates factorial of 5 using a clocked process.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Fibonacci is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        fib_out : out INTEGER_VECTOR(0 to 9)
    );
end Fibonacci;

architecture Behavioral of Fibonacci is
    signal fib : INTEGER_VECTOR(0 to 9);
begin

    process(clk, reset)
    begin
        if reset = '1' then
        fib(0) <= 0;
        fib(1) <= 1;
        elsif rising_edge(clk) then
        for i in 2 to 9 loop
        fib(i) <= fib(i-1) + fib(i-2);
        end loop;
        end if;
    end process;

    fib_out <= fib;
end Behavioral;

Generates first 10 Fibonacci numbers using signals and an array.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity MaxProgram is
    Port (
        a : in INTEGER;
        b : in INTEGER;
        max_out : out INTEGER
    );
end MaxProgram;

architecture Behavioral of MaxProgram is
begin
    process(a, b)
    begin
        if a > b then
        max_out <= a;
        else
        max_out <= b;
        end if;
    end process;
end Behavioral;

Finds the maximum of two input numbers.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ArraySum is
    Port (
        sum_out : out INTEGER
    );
end ArraySum;

architecture Behavioral of ArraySum is
    type int_array is array (0 to 4) of INTEGER;
    signal nums : int_array := (1,2,3,4,5);
    signal sum : INTEGER := 0;
begin
    process(nums)
    begin
        sum <= 0;
        for i in 0 to 4 loop
        sum <= sum + nums(i);
        end loop;
    end process;

    sum_out <= sum;
end Behavioral;

Sums elements of a fixed array.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity EvenNumbers is
    Port (
        evens_out : out INTEGER_VECTOR(0 to 4)
    );
end EvenNumbers;

architecture Behavioral of EvenNumbers is
    signal nums : INTEGER_VECTOR(0 to 9) := (1,2,3,4,5,6,7,8,9,10);
    signal evens : INTEGER_VECTOR(0 to 4);
begin
    process(nums)
        variable idx : INTEGER := 0;
    begin
        idx := 0;
        for i in 0 to 9 loop
        if nums(i) mod 2 = 0 then
        evens(idx) <= nums(i);
        idx := idx + 1;
        end if;
        end loop;
    end process;

    evens_out <= evens;
end Behavioral;

Outputs even numbers from a fixed array.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ConcatStrings is
    Port (
        result_out : out STRING(1 to 10)
    );
end ConcatStrings;

architecture Behavioral of ConcatStrings is
    signal str1 : STRING(1 to 5) := "HELLO";
    signal str2 : STRING(1 to 5) := "WORLD";
    signal result : STRING(1 to 10);
begin
    process(str1, str2)
    begin
        result <= str1 & str2;
    end process;

    result_out <= result;
end Behavioral;

Concatenates two strings using '&' operator.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ConditionalIncrement is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        count_out : out INTEGER
    );
end ConditionalIncrement;

architecture Behavioral of ConditionalIncrement is
    signal count : INTEGER := 3;
begin
    process(clk, reset)
    begin
        if reset = '1' then
        count <= 3;
        elsif rising_edge(clk) then
        if count < 5 then
        count <= count + 1;
        end if;
        end if;
    end process;

    count_out <= count;
end Behavioral;

Increment counter only if below 5.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ConditionalIncrement is
    Port (
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        count_out : out INTEGER
    );
end ConditionalIncrement;

architecture Behavioral of ConditionalIncrement is
    signal count : INTEGER := 3;
begin
    process(clk, reset)
    begin
        if reset = '1' then
        count <= 3;
        elsif rising_edge(clk) then
        if count < 5 then
        count <= count + 1;
        end if;
        end if;
    end process;

    count_out <= count;
end Behavioral;

Increment counter only if below 5.