2-bit Counter with Reset - Systemverilog Typing CST Test
Loading…
2-bit Counter with Reset — Systemverilog Code
A synchronous 2-bit counter with asynchronous reset.
module Counter2Bit(
input logic clk,
input logic reset,
output logic [1:0] count
);
always_ff @(posedge clk or posedge reset) begin
if (reset)
count <= 2'b00;
else
count <= count + 1;
end
endmoduleSystemverilog Language Guide
SystemVerilog is a hardware description and verification language (HDVL) that extends Verilog with advanced features for hardware modeling, simulation, and verification in digital design.
Primary Use Cases
- ▸RTL modeling of digital circuits
- ▸Functional verification using testbenches
- ▸Formal verification with assertions
- ▸Constrained-random stimulus generation
- ▸Coverage-driven verification of complex designs
Notable Features
- ▸Class-based object-oriented programming for verification
- ▸Constrained random stimulus generation
- ▸Functional coverage and assertions
- ▸Interfaces and modports for modular designs
- ▸Enhanced data types (logic, bit, enum, struct, union)
Origin & Creator
Developed by Accellera and later standardized as IEEE 1800, SystemVerilog builds upon Verilog (originally created by Phil Moorby in 1984) to unify design and verification features.
Industrial Note
SystemVerilog is essential in high-performance semiconductor industries for complex SoC verification, coverage-driven testbenches, and constrained-random simulation.