2-bit Counter - Chisel-hdl Typing CST Test
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2-bit Counter — Chisel-hdl Code
A simple 2-bit synchronous counter using Chisel.
import chisel3._
class Counter2Bit extends Module {
val io = IO(new Bundle {
val count = Output(UInt(2.W))
})
val cnt = RegInit(0.U(2.W))
cnt := cnt + 1.U
io.count := cnt
}
object Counter2Bit extends App {
chisel3.Driver.execute(args, () => new Counter2Bit)
}Chisel-hdl Language Guide
Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware description language embedded in Scala. It provides a modern, object-oriented approach to designing digital circuits and generating synthesizable Verilog for FPGAs and ASICs.
Primary Use Cases
- ▸Designing parameterizable digital modules
- ▸Creating reusable hardware generators for CPUs and peripherals
- ▸Rapid prototyping for FPGA development
- ▸Integration with simulation and verification frameworks
- ▸Generating synthesizable Verilog for ASIC and FPGA flows
Notable Features
- ▸Embedded DSL in Scala for hardware design
- ▸Supports parameterized and modular generators
- ▸Strong type system with compile-time checks
- ▸Integrated with FIRRTL for intermediate representation
- ▸Testing and simulation tools for functional verification
Origin & Creator
Developed at UC Berkeley by the Berkeley Architecture Research group to modernize hardware design with high-level programming abstractions, leveraging Scala’s features.
Industrial Note
Essential for hardware architects and FPGA/ASIC designers who want reusable, parameterizable, and maintainable RTL generators, reducing manual Verilog coding and improving design productivity.