Learn SYSTEMVERILOG with Real Code Examples

module LED_Blink(
    input logic clk,
    output logic led
);

logic [23:0] counter = 0;

always_ff @(posedge clk) begin
    counter <= counter + 1;
    led <= counter[23];
end

endmodule

Toggle an LED using a clock divider with SystemVerilog syntax.

module AND_Gate(
    input logic A,
    input logic B,
    output logic Y
);

assign Y = A & B;

endmodule

Implement a simple 2-input AND gate using SystemVerilog.

module Counter2Bit(
    input logic clk,
    input logic reset,
    output logic [1:0] count
);

always_ff @(posedge clk or posedge reset) begin
    if (reset)
        count <= 2'b00;
    else
        count <= count + 1;
end

endmodule

A synchronous 2-bit counter with asynchronous reset.