Learn VHDL with Real Code Examples

Learn basic syntax, entities, architectures

Build combinational logic blocks

Work with FSMs and sequential circuits

Write testbenches

Synthesize on FPGA boards

Week 1: Entities/architectures

Week 2: Processes and signals

Week 3: FSMs & datapaths

Week 4: FPGA synthesis & timing

Difference between signal and variable?

Explain entity/architecture.

Blocking vs non-blocking equivalents?

How do sensitivity lists work?

What constructs are synthesizable?

entity NAME is ... end;

architecture RTL of NAME is ... end;

signal X : std_logic;

process(clk) begin if rising_edge(clk) then ... end if; end process;

<= for signals, := for variables

VHDL Primer by Bhasker

Circuit Design with VHDL by Pedroni

The Designer’s Guide to VHDL

Fundamentals of Digital Logic with VHDL

VHDL basics for beginners

FPGA design with VHDL

Testbench writing tutorials

Advanced VHDL design patterns

IEEE 1076 VHDL Standard

IEEE Numeric_Std Documentation

GHDL & Vendor Tool Docs

EDA forums

StackOverflow VHDL tag

GHDL and FPGA communities

Reddit r/FPGA

Vendor support forums

VHDL GitHub communities

EDA forums

StackOverflow VHDL tag

GHDL community

FPGA vendor forums