Learn Chisel-hdl - 3 Code Examples & CST Typing Practice Test
Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware description language embedded in Scala. It provides a modern, object-oriented approach to designing digital circuits and generating synthesizable Verilog for FPGAs and ASICs.
View all 3 Chisel-hdl code examples →
Learn CHISEL-HDL with Real Code Examples
Updated Nov 27, 2025
Code Sample Descriptions
Blink LED Module
import chisel3._
class BlinkLED extends Module {
val io = IO(new Bundle {
val led = Output(Bool())
})
val counter = RegInit(0.U(24.W))
counter := counter + 1.U
io.led := counter(23)
}
object BlinkLED extends App {
chisel3.Driver.execute(args, () => new BlinkLED)
}
Toggle an LED using a simple counter in Chisel.
2-bit Counter
import chisel3._
class Counter2Bit extends Module {
val io = IO(new Bundle {
val count = Output(UInt(2.W))
})
val cnt = RegInit(0.U(2.W))
cnt := cnt + 1.U
io.count := cnt
}
object Counter2Bit extends App {
chisel3.Driver.execute(args, () => new Counter2Bit)
}
A simple 2-bit synchronous counter using Chisel.
2-input AND Gate
import chisel3._
class AndGate extends Module {
val io = IO(new Bundle {
val A = Input(Bool())
val B = Input(Bool())
val Y = Output(Bool())
})
io.Y := io.A & io.B
}
object AndGate extends App {
chisel3.Driver.execute(args, () => new AndGate)
}
Implement a 2-input AND gate in Chisel.
Frequently Asked Questions about Chisel-hdl
What is Chisel-hdl?
Chisel (Constructing Hardware in a Scala Embedded Language) is a hardware description language embedded in Scala. It provides a modern, object-oriented approach to designing digital circuits and generating synthesizable Verilog for FPGAs and ASICs.
What are the primary use cases for Chisel-hdl?
Designing parameterizable digital modules. Creating reusable hardware generators for CPUs and peripherals. Rapid prototyping for FPGA development. Integration with simulation and verification frameworks. Generating synthesizable Verilog for ASIC and FPGA flows
What are the strengths of Chisel-hdl?
High-level, expressive syntax reduces repetitive RTL coding. Strong typing prevents many hardware design bugs at compile time. Parameterizable designs improve code reuse and scalability. Integration with modern software tooling (Scala ecosystem). Supports verification through ChiselTest and simulation
What are the limitations of Chisel-hdl?
Requires knowledge of both hardware design and Scala. Tooling and ecosystem smaller than traditional Verilog/VHDL. Debugging generated Verilog can be challenging. Longer learning curve for engineers with only RTL experience. Simulation performance may lag compared to low-level RTL simulators
How can I practice Chisel-hdl typing speed?
CodeSpeedTest offers 3+ real Chisel-hdl code examples for typing practice. You can measure your WPM, track accuracy, and improve your coding speed with guided exercises.